package Core.gencpu

import Core.{CPUSimple, CPUSimpleConfig}
import Core.ip.{DCacheConfig, ICacheConfig}
import Core.plugin._
import Core._
import spinal.core._
import spinal.lib._

object Config {
    def spinal = SpinalConfig(
        targetDirectory = "src/gen",
        defaultConfigForClockDomains = ClockDomainConfig(
            resetActiveLevel = HIGH
        ),
        onlyStdLogicVectorAtTopLevelIo = true,
        nameWhenByFile = false,
        genLineComments = true,
        anonymSignalPrefix = "tmp"
    )
}

object GenSimple extends App{
    def cpu() = new CPUSimple(
        config = CPUSimpleConfig(
            plugins = List(
                new FetchPlugin(addressWidth = 32),
                new DecodePlugin,
                new BPUPlugin(p = PredictorConfig(
                    addressWidth =32,
                    RAS_ENTRIES = 4,
                    BTB_ENTRIES = 4,
                    PHT_ENTRIES = 128
                )),
                new AluPlugin,
                new ControlPlugin,
                new ExcepPlugin,
                new LsuPlugin(AW = 32, DW = 32),
                new ICachePlugin(config = ICacheConfig(
                    cacheSize = 32*1024, // 32KB
                    // cacheSize = 1*1024, // 1KB
                    bytePerLine =64,
                    wayCount = 4,
                    // addressWidth = 64,
                    addressWidth = 32,
                    cpuDataWidth = 32,
                    bankWidth = 32,
                    busDataWidth = 64,
                    directOutput = true,
                    noBurst=true
                )),
                new DCachePlugin(config = DCacheConfig(
                    // cacheSize = 32*1024, // 32KB
                    // cacheSize = 1*1024, // 1KB
                    cacheSize = 512, // 512B
                    bytePerLine =64,
                    wayCount = 2,
                    // addressWidth = 64,
                    addressWidth = 32,
                    cpuDataWidth = 32,
                    bankWidth = 32,
                    busDataWidth = 64,
                    directOutput = true,
                    // noBurst=false
                    noBurst=true
                ))
            )
        )
    )
    Config.spinal.generateVerilog(cpu())
}
